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3I5KC
rBLANKWGl COMPSYNC.
' H HOR.DRIVE h
[VERT.DRIVEj
Fig. 12. Synchronizing pulse generator block diagram.
MAIN DIVIDER
3I.5KC
60~
OUTPUT
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AF
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315 K.C. MASTER OSC.
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REF FREQ.
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3I.5KC TO MAIN
DIVIDER
Fig. 13. Master oscillator block diagram.
addition to the a-c line voltage. A linetap switch allows operations over an input supply range of 95 to 130 v. The power consumption of a complete chain is approximately 1000 w.
The synchronizing pulse generator is packaged as a completely self-contained unit. The circuits are built on standard rack panels and, when rack-mounted, the complete synchronizing pulse generator with power supply requires only 31 in. of rack space, yet operational stability is such that only three controls need be provided. The synchronizing pulse generator, open for servicing, is shown in Fig. 1 1 .
A simplified block diagram of the synchronizing pulse generator is shown in Fig. 12. The master oscillator operates
at 31.5 kc. From this is derived a pulse at 60-cycle rate by means of the 525 : 1 divider, and a pulse at 15.75 kc by means of the 2 : 1 divider. These two pulses are fed to the synchronizing and blanking pulse generator circuits and are used to generate the desired output waveforms. These are the complete synchronizing signal, mixed blanking signal, and horizontal and vertical drive pulses. All four waveforms are available in either positive or negative polarity at a level of 4 v.
A block diagram of the master oscillator chassis is shown in Fig. 13. A twin triode, 31.5-kc oscillator, which provides excellent stability, is used. An AFC circuit allows the oscillator to be locked to the 60-cycle power line or to an
176
February 1953 Journal of the SMPTE Vol.60